1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a semiconductor memory device having the scheme that effectively operates a nonvolatile memory structure.
2. Description of the Related Art
Among the integrated semiconductor memories mounted in LSI are nonvolatile memories, which are an element that retains stored information even after power to the LSI has been turned off. In this context, nonvolatile memories are a very important element for using LSI in various applications.
Regarding semiconductor nonvolatile memory devices, so-called floating-gate memories and the memories that use insulating films are described in the publication “Physics of Semiconductor Devices, 2nd edition” written by S. Sze, published by Wiley-Interscience Pub, pp. 496–506. The following is known in the art as described therein: Compared with the floating-gate type, the type of memory having a stack of insulating films and storing electric charges in the traps at their interface or of the insulating films can be formed in a process very consistent with a CMOS LSI process, since there is no need to form an additional electroconductive layer.
The conventional type that stores charges in the insulating films, however, is difficult to realize, since this type is required to have sufficient charge-holding characteristics while at the same time injecting and releasing the charges. A memory that updates stored information by injecting charges of different polarities, instead of releasing stored charges, is proposed in contrast to the above type. The operation of this memory is described in “1997 Symposium on VLSI Technology”, 1997, pp. 63–64. In this memory cell structure, a polycrystallized silicon gate for operating the memory, and a gate for selecting cells are separately formed. A similar description is also given in U.S. Pat. Nos. 5,969,383 and 6,477,084.
In this memory cell structure, two transistors based on NMOS, namely, a memory transistor and a select transistor, are placed next to each other so as to be interconnected in the so-called “series connection” arrangement. This transistorized circuit is shown as an equivalent circuit in FIG. 1C. A plan view and sectional view of a memory element associated with the circuit shown in FIG. 1C are shown in FIGS. 1A and 1B, respectively. A configurational example of forming an array using such memory cells is shown in FIG. 2. The select transistor and memory transistor gates (the select gate and the memory gate) constitute the word lines shown as SGL and MGL, respectively. Also, the diffusion layer of the select transistor is shown as a bit line (BL), and the diffusion layer of the memory transistor is shown as a source line (SL).
Typical programming/erasing operation in this memory cell structure is shown in FIGS. 3 and 4. The gate-insulating film 950 of the memory gate is formed to have a structure in which a silicon nitride film is sandwiched between silicon oxide films. This structure is so-called the MONOS structure (Metal-Oxide-Nitride-Oxide Semiconductor (Silicon)). The gate-insulating film 900 of the select gate is a silicon oxide film. The diffusion layer electrodes 200, 300 are formed with the select gate and the memory gate as the respective masks. The conceivable basic modes of operation in this memory cell structure are: (1) programming, (2) erasure, (3) hold, and (4) readout.
However, these designations of the four modes are typical ones and programming and erasure can be designated inversely. Although typical methods of operations are also described hereunder, other different methods of operations are proposed. An NMOS-type memory cell structure is described below for the sake of convenience in the description. However, a PMOS type can also be formed on the same principles of operation.
The state during (1) programming is schematically shown in FIG. 3. The diffusion layer 200 of the memory gate is given a positive potential, and the diffusion layer 300 of the select gate is given the same grounding potential as that of a substrate 100. The channel under the memory gate 550 can be turned on by applying thereto a high gate-overdriving voltage relative to the voltage of the substrate 100. More specifically, the channel can be turned on by increasing the potential of the select gate by 0.1–0.2 V above its threshold level. At this time, since the strongest electric field occurs near the boundary of the two gates, a number of hot electrons occur and are injected into the memory gate. The way a carrier is generated by impact ionization is denoted by reference numeral 800 in the figure. The non-hatched circle denotes an electron, and the hatched circle denotes a positive hole. The occurrence event of the carrier is known as source-side injection (SSI), which is described in the report of A. T. Wu et al. in “1986 IEEE, International Electronic Device Meeting, Technical Digest”, 1986, pp. 584–587. Although memory cells of the floating-gate type are described in this report, the insulating-film type also employs the same injection mechanism. Hot-electron injection in this scheme features intensive injection into the select gate end of the memory gate because of an electric field being concentrated on the neighborhood of the boundary between the select gate and the memory gate. Also, while the floating-gate type has its charge-holding layer constituted by electrodes, the insulating-film type has electrons held in very narrow regions since the electrons are stored into the insulating films. The state during (2) erasure is schematically shown in FIG. 4. Applying a negative potential to the memory gate 550 and a positive potential to the diffusion layer 200 of the memory gate causes strong inversion in the region overlying the diffusion layer and the memory gate at the end of the diffusion layer. The strong inversion then causes tunneling between bands, thus generating holes. This condition is shown in FIG. 10. Such inter-band tunneling is described in, for example, the report of T. Y. Chan et al. in “1987 IEEE, International Electronic Device Meeting, Technical Digest”, 1987, pp. 718–721. In this memory cell structure, generated holes are accelerated in the direction of the channel and then electrically attracted and injected into the MONOS films by the bias of the memory gate, whereby the erasing operation is conducted. The way the generated holes cause a positive-hole pair as secondary electrons is denoted by reference numeral 820. These carriers are also injected into the MONOS films. That is to say, the threshold levels of the memory gate that have been raised by the charges of the electrons can be lowered by means of the charges of the injected holes.
During (3) hold, charges are held as those of the carriers which were injected into the insulating films of MONOS. Since the quantities of the carriers migrating inside the insulating films are very small and the migration is slow, the charges can be efficiently held, even when a voltage is not applied to the electrodes.
During (4) readout, the channel under the select gate 500 can be turned on by applying a positive potential to the diffusion layer 200 of the select gate and another positive potential to the select gate. In this case, held charge information can be read out as a current by applying a suitable memory gate potential that allows the identification of the difference between the threshold levels of the memory gate that are given in programming and erasure modes (namely, an intermediate potential between the threshold levels in both modes).